Design and VLSI implementation of SRAM memory array using Application-specific Integrated circuits design flow

Abstract

Static Random-access memory (SRAM) are useful structure blocks in operations like data storage, embedded operations, cache recollections, microprocessors. The circuits should retain larger impunity to noise voltages. So, the Stationary Noise Margin (SNM) of the circuits should be veritably high. Large SRAM arrays that are extensively used as cache memory in microprocessors and operation-specific integrated circuits can absorb a big portion of the chip area. Highly compact circuits like SRAM arrays are estimated to cover relatively 90% of the System on chip area within the coming years. To optimize the performance of similar chips, large arrays of fast SRAM help to speed up the system performance. As a result, numerous minimal-size SRAM cells are tightly packed making SRAM arrays the compact circuitry on a chip. In this work an attempt is made to design a 8 X 8 SRAM memory array along with different components like Write driver circuit, Pre-charge circuit, Row and Column Decoder. Different SRAM architectures such as 6T, 7T and 8T are designed and different parameters such as Static Noise Margin and power dissipated are measured and the best performing memory design has been selected. 8T design has been resulted with least power dissipation. Hence this cell is selected for designing the memory array. A schematic of 8 x 8 array is designed and the layout of single SRAM 8T is created and to complete the ASIC design flow, DRC is done and the pre and post simulation are compared and verified. The integrated SRAM is operated with an input voltage of 0 to 1.8V.

Introduction

I. INTRODUCTION

Memory is a component that holds the state of a task for the duration it is needed. It is a block that holds the data and instructions that are needed by the CPU for execution. Static random access memory (SRAM) is a volatile memory present onchip. It is mainly used as cache memory. With the advent of technology, a large number of research is being conducted to reduce the power and area and increase the memory cell’s stability. There is a dire need to know the one that best suits the application with the various architectures present. There is no single architecture that can suit the designer’s need, it boils down to the kind of application that is being designed, and the various constraints like area of the chip, the power dissipated etc. are being taken into account before determining the kind of memory that is needed. This report presents a detailed comparative study on the 3 different SRAM memory architectures. A 8T SRAM with its layout and its back annotation is done.

Static Random Access Memory (SRAM) is a type of volatile memory that is commonly used in digital electronics applications to store small amounts of data. The design of an SRAM involves creating a circuit that is capable of storing and retrieving data quickly and reliably. The main challenge in designing an SRAM is to balance the conflicting requirements of high speed, low power consumption, and small area. The circuit must also be able to operate reliably over a wide range of operating conditions such as temperature and supply voltage. Additionally, the design must take into account factors such as the number of memory cells required, the access time, the power consumption, and the overall cost. Therefore, the design of an SRAM involves careful consideration of various tradeoffs and optimization techniques to ensure that the resulting circuit meets the desired specification

II. THEORETICAL   BACKGROUND

Static Random Access Memory (SRAM) is a type of volatile memory that is widely used in digital electronic devices, such as computers and mobile phones, for storing data that needs to be accessed frequently and quickly. SRAMs are typically implemented as arrays of memory cells, each consisting of a flip-flop circuit that can store one bit of data.

Designing and implementing an SRAM memory array using Application-specific Integrated Circuits (ASICs) design flow involves several stages, including:

1. Specification and Architecture Design: In this stage, the specifications and requirements of the SRAM memory array are defined. This includes the number of memory cells, the size of each cell, the data access time, the power consumption, and other parameters. The architecture of the memory array is also designed, which involves selecting the type of memory cell, the number of rows and columns in the array, and the organization of the memory.
2. Circuit Design: In this stage, the individual circuits that make up the SRAM memory array are designed. This includes designing the flip-flop circuits that store the data, the bit-line and word-line circuits that enable data access, and the sense-amplifier circuits that amplify the signals from the memory cells.
3. Layout Design: In this stage, the physical layout of the SRAM memory array is designed. This involves placing the individual circuits on the chip, routing the interconnections between the circuits, and optimizing the layout for performance and reliability.
4. Verification: In this stage, the design is verified to ensure that it meets the specifications and requirements. This includes simulating the circuit behavior, testing the layout for timing and signal integrity, and verifying the functionality of the memory array.
5. Fabrication: In this stage, the ASIC chip is fabricated using semiconductor manufacturing processes. This involves creating the silicon wafer, depositing and patterning the layers of materials that make up the circuits, and testing the functionality of the chip.
6. Testing and Characterization: In this stage, the fabricated chip is tested to ensure that it meets the specifications and requirements. This includes testing the functionality of the SRAM memory array, measuring the timing and power characteristics, and characterizing the chip for reliability and yield.

III. DESIGN AND IMPLEMENTATION

A. Design for Implementation SRAM memory array

1.  RAM Array: Includes SRAM bit cells which should occupy minimum area to achieve cell density i.e number of 1bit SRAM cells per unit area should be as high as possible.
2. Decoder: Memory cell matrix consists of rows and columns. Each row is accessed through word line while each column is accessed through bit line. Data lines are responsible for transferring data to and from bit lines depending upon write and read operation respectively. Generally, by making word line high entire word is obtained. So, column decoder is used to distinguish among columns.
3. Sense Amplifiers: Bit stored in a memory cell is determined by the voltage across bit lines. However, due to large number of cells connected to a column circuitry, it is difficult to get a proper output. Therefore, sense amplifiers are used as it gives stability and reliability to circuitry.
4.  Pre-charge circuit: Before every read and write operation, pre-charge becomes high and both bit lines are charged to a value Vdd/2. During pre-charge and equalizer cycle, both bit lines are shorted so that voltage difference across them is zero. When pre-charge is off and sense amplifier turns on, it senses small voltage difference between two bit lines and accordingly stores a bit in memory cell.
5. Read Write Circuit: The read-write circuit in SRAM is responsible for reading and writing data to and from the memory cell. It consists of a sense amplifier, write driver, and bitlines. During a read operation, the sense amplifier senses the voltage difference between the bitlines and amplifies it to determine the stored data. During a write operation, the write driver applies a voltage to the bitlines to write the desired data into the cell. The read-write circuit operates at high speed and low power to ensure efficient operation of the SRAM.

B. Circuit Description

1. Decoder: It is just a combinational circuit that converts binary information from n input lines to maximum of 2n unique outputs. Enable inputs must be on for the decoder to function otherwise its outputs assume a single “disabled” output code word. With this the binary input conversion gets easier with the operation and we need for the desired output from this kind of combinational output by which we can use it for no of operations like data, word line selection for the memory cell. And also for the other digital information storage working.

2. Pre Charge Circuit: Sense amplifier are the vital component in the memory design. The job of sense amplifier is to sense the bit line for proper monitoring action. It improves the read and write speed of the memory cell. Its another job is to reduce the power needed for the operation. The sense amplifiers primary job is to amplification of the voltage is being produced on the bit line at the time of operation. As it has the important job in the memory so it has different circuits for the operation. As we know that in SRAM operation we don’t need refresh of the memory for the further process, so the sense amplifiers non destructive at the time of operation. As the column multiplexers are connected in the memory cell at that time multiplexer should choose one sense amplifier for the single input. So that we can get proper use of the sense amplifier in the designing circuit. These are the various parameters of an sensing amplifier

Gain A = Vout/Vin.

 Sensitivity S =vin min - least noticeable sign

3. Read Write Circuit: The read-write circuit in SRAM is responsible for the critical task of reading and writing data from and to the memory cell. The circuit consists of several components, including the bitlines, write driver, sense amplifier, and control logic i.e write enable. During a read operation, the control logic activates the wordline corresponding to the desired memory cell, which in turn drives the stored data onto the bitlines. The sense amplifier then amplifies and compares the voltage difference between the bitlines to determine the stored data. During a write operation, the control logic activates the wordline and applies the desired data to the bitlines using the write driver. The stored data in the memory cell is then updated based on the voltage level on the bitlines. The read-write circuit operates at high speed and low power to ensure efficient operation of the SRAM. The sense amplifier and write driver consume most of the power in the circuit and are designed to operate quickly to minimize the time required for data access.

D. 8x8 SRAM Memory Array

A 8 x 8 memory array is designed using the 8T as the base memory cell. Two Decoders – Row Decoder and Column Decoder are also designed. Initially the output of the row decoder was connected with the word line of the cells of each row. The column decoder was connected with the bit line and an internal inverter was used to give the negated value to the bitline bar. Some of the problems faced with this design were as follows

• During the write operation for a particular cell, the word line for the entire row would be high. Therefore, since all the other outputs of the column decoder would be 0, all the remaining cells would be refreshed and hence all the data would be lost.
• While selecting a particular cell, the corresponding row decoder and column decoder lines has to be high, by doing so we can write a logic “1” into the cell. But it is not possible to write a logic “0” with this design.
• Hence if the column decoder line should not be used as the bit line, but then the selection of a particular cell to read or write would not be possible. Hence to overcome all these problems we have added an AND gate whose inputs would be from the row and column decoder lines and the output of the AND gate would go to the word line of respective cells. All the bit lines of all the memory cells are shorted together, hence whatever value has to be written into the cells will be given into this bit cell and the value will be written to only that particular cell whose row decoder and column decoder lines are high hence enabling their word line. With these changes in the design all the above stated problems have been solved.

Conclusion

This work compares different SRAM cell architectures along with their various parameters. A 8T cell is designed which outperforms the standard SRAM cells in terms of the power dissipated by the source. The major focus of this work was to compare the Static Noise Margin and Power dissipated of each of the cells. There is no single architecture that can be concluded to be the best suited for every application. 8T can be intuitively chosen for low power applications, as it consumes less power as compared with the other architectures and also has a similar comparable snm as the other architectures, which makes it suitable for highly accurate and reliable applications. There always exists a trade-off in every cell and it boils down to the liability of the designer to choose the one that fits best for the specific application.

References

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Copyright

Copyright © 2023 Akshay J A, Amith Chavan R, Chethan S P, Dr. S V Sathyanarayana. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.